Advanced mobile devices drive Display segment growth

The demand for increasingly high-resolution, power-efficient display screens for mobile devices is increasing quickly, as the above chart shows. It should be a major growth driver for the Display segment. Screen resolution is an important differentiator in the selection of devices and appliances, leading to significant growth in high-definition screens.

Until a few years ago, most LCDs used transistors made with amorphous silicon. However, as displays evolve to higher densities, LCD manufacturers are pressured to switch to higher mobility polysilicon transistors in order to scale to smaller dimensions at low power levels. The retina display on Apple’s (AAPL) iPhone was fabricated with low-temperature polysilicon (or LTPS). Samsung (SSNLF) followed the same design for its OLED displays. The company expects multiple Gen 6 LTPS factories to be built in the next year or two to support this demand.

The major difference is the size of the mother glass that is used at the very beginning of the manufacturing process. From the birth of the industry in early 1990's, the Japanese creators began with generation one (G1) technology processing. The mother glass used in G1 was approximately 30cm x 40cm, equivalent to the size of an open fashion magazine and could make one 15" panel. When Acer Display Technology Inc., which subsequently merged with Unipac Optoelectronics Corp. to form AUO, entered the industry in 1996, the technology had already advanced to G3.5 with the 60cm x 72cm mother glass size. Also, the gigantic mother glass of AUO's G7.5 fab has dimensions of 195cm x 225cm . Its larger scale can cut up to eight 42" or six 47” flat panels per manufacturing process. The capacity of AUO's G7.5 line in Taichung has reached 60,000 on monthly glass substrate input since Q3 2007. AUO also plans the next G7.5 / G8.5 hybrid fab, the mother glass used in G8.5 is approximately 220 x 250 cm, equivalent to the size of a pool table, but the glass thickness is less than 1mm. Therefore, the new generation fab require higher process technology. The mother glass of AUO's G8.5 fab can be cut to six 55” or eight 46” flat panels per manufacturing process, mainly used to produce 46” and above large scale panel.

As technologies for large-sized panels become increasingly mature, AUO will continuously focus on the development of next-generation fabrication, aiming to increase capacity, manufacturing quality and offering better customer service

Advantages of AUO LTPS Technology

The process of LTPS is far more complex than a-Si. On the other hand, the carrier mobility in LTPS TFT is 100 times (>100 cm2/V‧s) higher than that in a-Si TFT. In addition, LTPS allows CMOS processes directly on the glass substrate. The following are several aspects that p-Si is superior to a-Si:

Slim border: Conventional amorphous silicon display structure requires two or three edges on the frame to accommodate the driver IC, which makes slim border difficult. On the other hand, LTPS can directly integrate the drive circuits onto the glass substrate, which facilitates a slim border and high picture quality for the panel. In addition, the integration circuit of LTPS requires fewer number of external signal connections, which reduces the module components by 40% and effectively lowers the cost. Compact module: Since part of the drive circuit can be fabricated on the glass substrate, the PCB circuit can be relatively simple and saves more PCB area. High aperture ratio and high resolution: High mobility means smaller geometry of transistors are capable of providing sufficient charging power and higher capacitance than conventional amorphous silicon, which translates to a larger effective area transmitted by light. Take the 2-inch QVGA by AUO as an example, since its aperture ratio is as high as 58%, the number of backlight LEDs can be reduced, enabling cost reduction and energy saving, which is suitable to applications for cell phones or mobile devices. Vehicle for OLED: Organic Light-Emitting Device (OLED) display has advantages such as fast response time, light weight, low power, and wide viewing angle. Compared to a conventional LCD, the drive method of OLED is a special current drive structure. In addition, the compensation circuit designed to overcome gray scale and achieve panel uniformity requires using two to six TFTs in one pixel. With the high-density layout characteristic of LTPS, an OLED display panel with high brightness and high picture quality can be easier to achieve. Meanwhile, the lifetime of OLED can be extended. High mobility means more current can be provided to the OLED device, which is more suitable to be used as the substrate of active OLED display.

Applications of AUO LTPS Technology

With the fast development of consumer electronics products, AUO LTPS display products feature light weight, slim, low power, high resolution and high performance have been extensively implemented to various products such as smart phone, PDA, navigation system, digital still camera (DSC), etc.

At present, the mainstream high-end LTPS products of AUO boast of a resolution as high as 270ppi. The contrast can reach 1000:1 if combined with the AUO PSA (polymer stabilized alignment) technology. It is also compatible with the touch panel technology and is suitable for applications such as smart phone or high-end DSC.

圖片說明 AUO LTPS 3吋面板高解析度產品 解析度 : 270PPI 開口率 : 50% 窄框化 : 1.8mm 對比 : 1000 : 1

Conclusion

The design rules for low-temperature poly-silicon (LTPS) are less stringent than those for the conventional amorphous TFT and have the advantages of high aperture ratio and high resolution. The load on the backlight system can be relieved by increasing the transmittance, which extends the lifetime of the LTPS panel. However, LTPS TFT is subject to drifting and non-uniformity caused by grain boundary number and location arising from LTP scaling. To prevent the grain boundary of poly-silicon from affecting the carrier mobility, the development of the next generation LTPS focuses on how to control the number of grain boundary, the crystalline orientations, and positions, to achieve no grain boundary in the silicon TFT channel. Many related crystallization techniques have been developed in this study, which include continuous silicon grain boundary, sequential lateral solidification, continuous-wave laser lateral crystallization, and selectively amplified laser crystallization. Moreover, more resources are needed for the research and development of the design and examination of LTPS. In addition to high-resolution panels, what really matters is the appropriate design of integration circuit functions. As a result, the future development of LTPS should focus on how to constantly seek added value for panels and innovations.

We get many organisations contacting us each week asking the question “Can you help us find new business?” In order to answer that question we ask them all four straight forward, simple questions – However many struggle to answer!

In order to illustrate each answer to the 4 questions, I’m going to pick one of the simplest products in the world – Water. However we’re going to pick two completely different brands of the same product, Carrick Glen© sold by Lidl© and Pellegrino©™ from Nestlé©. The price point is dramatically different, Carrick Glen©, works out at circa 21cents per litre and Pellegrino©™ works out at circa €2 per litre.

Each product appears the same but on reflection provides different functions and solve different problems.

The 4 questions are;

What problem does your product or service solve?

In other words, what real world problem does your product or service solve or help to solve?

Bottled water appears to solve the problem of thirst; I need to quench my thirst so I drink water – True. However why does one product which costs 10 times the price of the other, sell in such vast number? I argue STATUS. A bottle of Pellegrino©™ sitting on the table at a dinner party says ‘I’m prepared to spend 10 time the price on one brand because it helps to re-enforce my social and economic status in society’. I argue that Pellegrino©™ helps to solve the problem of ‘Status Anxiety’ or how we are perceived by others.

‘On the other hand’ Carrick Glen© offers a good tasting, value for money alternative to tap water. We’re a bit biased in the office, as we’re all fans of Carrick Glen©.

What’s you value proposition?

Value proposition, is the promise of value delivered by your product or service, perhaps the return on investment – ROI. If I spend €1,000 ‘I better be solving a problem costing more than €1,000′.

Using our two brands I would think the value proposition for Pellegrino©™ would way out perform the value proposition of Carrick Glen© – Social status for €2!

Who is your target market?

What does your ideal client look like; type, turnover, industry sector, number of employees or perhaps something intangible like ‘early adopter of technology’. Chances are if an organisation or person has a problem, similar types of organisations or persons will have the same problem. A problem you can solve.

Using our example, the consumers of Pellegrino©™ probably fall into the ABC1 social grade (upper middle class, middle class lower middle class). ABC1 consumers are prepared to pay more for their food as compared to the people in the lower social grades. I have to say I’m not a lover of categorising people along these lines but its fact of life.

What’s your differentiator?

What makes you different or what’s your USP – Unique Selling Point. This is very important in a world where there’s so much competition, you need to stand out from the crowd or be heard above the noise.

Pellegrino©™ is not only ‘posh water’ but its ‘posh Italian water’, arguably it sits head and shoulders above the other waters on the supermarket shelf.

So there you have it, the 4 Questions Every Company Needs to Answer. I feel these questions are important for every company to answer but this is especially true of start-ups, as they struggle to establish themselves.

More and more consumers want to have the world at their fingertips—literally—anytime, anywhere. Smart phones, e-book readers, multi-media tablets, and laptop computers are examples.

Ion Implanter Market Heats Up Increasingly precise tools are needed for 3D structures; vendors rush to fill the gap.

AUGUST 14TH, 2014 - BY: MARK LAPEDUS popularity The ion implanter market has been a stable, if not a sleepy, business. The last big event took place in 2011, when Applied Materials re-entered the ion implanter market by acquiring Varian, the world’s leading supplier of these tools. The acquisition gave Applied Materials a commanding 80% share of the implanter business, with the other players fighting for the crumbs.

But after years of stability, this market is heating up on two fronts. Ion implanters, one of the workhorse tools in the fab, are used to inject critical dopants into a device. Implanters enable the development of the source/drain and other portions of the chip.

In the market right now, Axcelis, the second largest supplier of ion implanters, is shipping a new line of tools in an effort to grab share from Applied Materials. In response, Applied Materials has introduced a new medium-current implanter to fend off Axcelis.

And on the technology front, the challenges for ion implantation are changing amid a shift toward finFETs and 3D NAND. In planar designs, the implanter generally injects dopants vertically into a substrate, which is a straightforward process. For finFETs, however, a tool must implant dopants at various and tough angles. The implanter, in turn, could miss the target, thereby impacting the uniformities, and yields, of a device.

So for finFETs and 3D NAND, next-generation implanters must be more precise and provide better dosage control, said Dennis Rodier, global product manager at Applied Materials. “Implant has always been a critical process step,” Rodier said, “but the requirements are becoming more demanding in the 3D world.”

And at 7nm and beyond, the challenges will escalate. For example, it may be difficult for implanters to inject dopants into tiny fins without leaving behind some damage. So, the industry is exploring a range of future options, such as hybrid tools that combine the advantages of deposition and implantation. Still others have developed futuristic transistors that eliminate the need for ion implantation all together.

Implanting the market In 2014, the ion implanter market is expected to grow slightly more than 10%, according to Gartner. The implanter market was just over an $800 million business in 2013. With an 80% share of the business, Applied Materials is also the leader in two of the three segments in the overall implanter market–high-current and medium-current. High-current implanters, which are used for source/drain development, represent about 55% of the total market. Medium-current tools, which are used for well implants, represent about 30%.

Axcelis, Nissin, SEN and Ulvac are the other players in the implanter market. Axcelis is the largest supplier in the third implanter segment — high-energy. High-energy implanters, which are used for deep well implants, represent 15% of the overall market.

“The number of implant steps requiring medium-current ion sources may grow faster than high-dose implant steps,” said David Christensen, an analyst with Gartner. “This is driven by the higher semiconductor logic component, with the shallow junctions preferentially driving the trend toward medium-current implants. We will also start to see high energy slow a bit.”

In the market right now, the big question is clear. With its new and impressive implanter line, can Axcelis close the gap against Applied? “Axcelis is in a much better position in 2014 and heading into 2015,” said Patrick Ho, an analyst at Stifel Nicolaus. “Now, does this mean we are going to see a large share shift from Applied to Axcelis? I do not believe this is the case. Axcelis is making gains, but I would not overstate it that a wholesale change is coming in the landscape. Still, chipmakers are happy that a more viable second source supplier is once again re-emerging to at least counter Applied Materials.”

Finding a happy medium In planar devices, the first major implant step takes place in the front-end-of-the-line (FEOL). In simple terms, a device undergoes a shallow trench isolation (STI) process, which, in turn, divides the chip into two parts. One part of the device is PMOS, while the other is NMOS. Both parts are injected with separate dopants, which are referred to as well implants. Following that step, annealing is used to activate the dopants.

Using a medium-current implanter, dopants such as arsenic and phosphorous are usually injected into PMOS, while boron may be used in NMOS. Typically, medium-current implanters have a maximum energy range of about 900keV (triple-charge), with dose ranges from E11 to E14.

Like planar, finFETs also require well implants using medium-current implanters. But conventional vertical or zero-degree implants won’t do the trick for finFETs. “Some of the implants require a higher degree of precision, especially with respect to angle control and accuracy. The other thing we’re seeing is that defect performance is becoming much more critical,” Applied’s Rodier said.

“If you look at the finFET design, you have the traditional well implant. You also have the ground plane,” Rodier said. “But more critically, you have these tuning implants such as Vt halo-like implants, similar to what you have in planar. From an implant perspective, you might end up with multiple threshold voltages that are required on a single chip.”

3D NAND is another emerging application for medium-current implanters. “If you are trying to dope the bottom of the channel, then the control becomes very critical for precise dosing of the base without affecting the sidewall,” he said. “So in many cases, customers are not looking for conformal type implants. But they are looking just to dope the base of the channel, which is very challenging. You must have a very high degree of angle precision to make that happen.”

Changes in high current Another important and separate implant step takes place in the formation of the source/drain part of a device. In planar devices, there are three basic implants—halo; source/drain extension; and final source/drain. Typically, those implants are provided by high-current implanters.

In finFETs, however, chipmakers possibly could eliminate some high-current implant steps. For source-drain doping, chipmakers could use in-situ doping during the epitaxial process, as opposed to implantation. Source/drain extension doping may still be done by delicate implants to avoid damage.

And for years, the industry has been looking at a process called plasma doping, which could displace high-current implanters. “The only company in production with finFET structures has used conventional high-current implanter systems to do source/drain implants on both of their first two generation nodes,” said Bill Bintz, executive vice president of marketing and engineering of Axcelis. “There was a lot of buzz about the use of plasma doping for finFET source/drains, but plasma doping technology has not been put to use for this application. As the finFET nodes progress and other IC manufacturers get into the game, new device fabrication challenges will continue to arise and alternative solutions will be investigated. To this end, plasma doping technology will continue to evolve as well as traditional ion implanter technology.”

In any case, the implants for the source/drain in finFETs must be delivered at precise angles. The big challenge is the so-called shadowing effect from the resists, which could impact the precision of the implants. “Historically, the most sensitive implant is the source-drain extension, sometimes called LDD or lightly doped drain implant. That was always zero degrees. If you had any cross wafer ion flux, variation or angular trajectory, you could just rotate the wafer and do a four-position implant at 90 degrees apart. So, in turn, you could average out that variation,” Bintz said. “With 3D structures, you are coming in at an angle. So for every pass of the wafer as you do an implant, you need to deliver a much tighter uniformity of the dose at an angle.”

Like medium- and high-current tools, high-energy implanters are finding new applications as well. “For deep isolation wells in NAND flash or image sensors, you need to go up to millions of volts. That’s where you need a high energy implanter,” he said.

What’s next? Besides the traditional applications, implanters are also moving into a new area called materials modification. “Customers are looking at implant technology to solve non-traditional challenges,” Bintz said. “For example, planarization is critical for finFETs. You have a dielectric. You want to make sure that it is planarized. There’s a lot of interest in using etch. For the etch application, people are looking at applying implant technology, where you would pattern the implant to alter the etch characteristics and take out the variation.”

And beyond 10nm, the industry is looking at new tool technologies. “Regarding implants for 7nm, the key challenge is getting high-level of dopants into the source/drain extension of the fins or nanowires without leaving behind damage or defects,” said Aaron Thean, director of the logic program at Imec. “We are working with key partners on new low-damage doping techniques that include modified ion implantations.”

In fact, Applied Materials, GlobalFoundries, Imec and SK Hynix recently described a new technology called Ion Assisted Deposition and Doping (IADD), which could be used for next-generation finFETs. Combining deposition and implantation techniques, IADD extracts ions from a plasma source, which are then directed onto the wafer. Then, the tool undergoes an ion assisted deposition process. The tool can provide about 6 knocked-in arsenic atoms for a 3-keV process at a 25 degree angle.

In another application, Nissin recently demonstrated a heated ion implantation technology for silicon-on-insulator finFETs. In the flow, the source-drain extension was formed at room temperature or heated using arsenic and other ions. Researchers enabled 20nm and 11nm thick SOI finFETs, which were perfectly crystallized by annealing.

Meanwhile, the leading next-generation transistor candidate is the gate-all-around FET. IBM recently described a gate-all-around silicon nanowire FET, which eliminated the need for ion implantation. Source-drain doping occurred during the epitaxial phase, according to IBM.

Does this all mean implanters are going away? Hardly. Implanters will be used for the foreseeable future. “I don’t see any show stoppers for us,” said Applied’s Rodier. “Certainly, there are no issues at 10nm. At 7nm, nobody fully understands what it will look like at this point. The industry doesn’t have a lot of visibility at 7nm and beyond.”

http://semiengineering.com/ion-implanter-market-heats-up/

Wafer Level Packaging enables rich graphics, high speed and low-power functionality in these mobile electronic end products. As these consumer products are becoming more mobility-enabled and multi-functional, they are also getting smaller and smaller. And users also expect these devices to have a longer battery life. Wafer-level packaging will enable sustained evolution of these mobile devices. Advanced packaging will also be a key to breaking through what has been called the “memory wall” or the limitation on processor performance that results from slower communication to the supporting memory chips. Advanced packaging makes the processor memory sub-system operate faster and more efficiently.

WHAT IS WAFER-LEVEL PACKAGING AND WHAT ISSUES DOES IT SOLVE?

The term describes processes performed at the wafer level (not die level) that deliver greater bandwidth or data handling capacity, using less power, in smaller and smaller end products. These processes have enabled the industry to evolve beyond wire-bonding to flip-chip packaging and through-silicon via (or TSV) technology.

In wire-bonding, chips are connected to a substrate using wires attached to the edges of the chip. Only so many wires can fit around the chip, which limits its data transfer capacity. Also, the wires are relatively long, which creates a timing lag and wastes power along the way. These wires have been getting smaller in diameter and closer together, which has stimulated a transition from wire-bond to flip-chip packaging. This transition has accelerated significantly as technology has scaled from 45nm to 28nm to 20nm.

In flip-chip packaging, wires are replaced with ‘bumps’ (i.e., connection points or pads) all over the top surface of the wafer to increase the areal density of electrical connections. When the wafer is diced (or cut up into pieces each containing a chip), the chips are turned over and attached to a substrate.

Where connectivity still poses a challenge, a redistribution layer (or RDL) containing conductive metal lines is also introduced to reroute connections on the die surface. The RDL also enables combination of different die functionalities in what is called a “system in package.”

In spite of these packaging approaches, however, when chips are placed and inter-connected on a board, they are connected by wires that are millimeters in length. This still limits the data-carrying bandwidth between them. And power consumption is still higher than is desirable.

Here is where TSV technology comes in. In TSV, vertical interconnects are running through the dies. This technology is used to connect chips on the same plane using a silicon interposer. A silicon interposer has TSVs running vertically and multiple layers of dense copper interconnects running horizontally. This technology, colloquially called 2.5D, can be used in servers, gaming consoles, and other high-performance systems. When TSV-enabled die are stacked on top of each other and interconnected with bumps (and RDL, if necessary), they form 3D integrated chips. This technology can be used for stacked DRAM, stacked NAND, or a processor-DRAM stack in mobile applications. TSVs have replaced peripheral wires that are millimeters in length with vertical connections that are just microns in length (1,000 times shorter).

These composite high-performance chip packages can be made from chips fabricated at the most cost-effective process node. They contain thousands, not hundreds, of inter-chip connections, enhancing their bandwidth. Connections are now microns long and are situated over the entire area of the chip, enabling faster data exchange and lower operating power.

In summary, TSVs offer all the attributes needed for today's mobile devices and cloud computing servers–greater functionality, faster operation, lower power consumption, longer battery life, and smallest volume. The dramatically increased bandwidth of multiple memory chips closely linked to multi-core central processing units demolishes the memory wall.

WHAT ROLE DOES APPLIED MATERIALS PLAY?

Applied Materials is the industry leader in wafer-level packaging, whose systems enable our customers to implement any of the above packaging techniques, from bumping to RDL to TSV. In addition to enabling the bump and RDL roadmap for technology and cost, we have spear-headed the industry’s development of TSV technology. Because of our work in this area, we are in a strong position to serve our customers as they begin to adopt this technology. We have designed new products and refined existing systems to address specific requirements for almost all of the steps in TSV fabrication. In addition, we have optimized the unit processes performed by our systems and have completed early cycles of learning on integrated process flows at our Maydan Technology Center in Sunnyvale, California. We are extending our work in this area with our new advanced packaging laboratory in Singapore.

On a broader scale, we have taken the lead in advancing collaboration between materials and equipment suppliers especially in new unit processes. We also work with R&D consortia to qualify an end-to-end process flow that offers the most cost-effective approach to commercializing TSV technology and accelerates our customers’ time to market. Within this framework of collaboration, Applied Materials will continue promoting the development of future wafer-level packaging technologies.

We’ve seen dramatic advances in only a few years. The power of a large computer just a few years ago is packed into a smartphone today. Mobile entertainment has become ubiquitous. And the story is far from over. Each time we think we are reaching the limits of technology, another breakthrough occurs. Wafer-level processing for packaging is one of the critical technologies that will keep the innovations coming for many years to come.

TSV FABRICATION PRODUCTS

Applied offers integration expertise and an extensive range of systems to enable widespread adoption of this important new chip packaging technology.

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http://www.appliedmaterials.com/files/introduction_3d_packaging.pdf

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How can we get a meeting with AMAT before the end of June?

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TSV offers product designers a new and highly space-efficient degree of freedom by enabling integration of circuit components from various nodes, boosting functionality and performance beyond those obtainable from wire bonding and flip chip 3D schemes.

In the drive to maximize the functionality-to-volume ratio, device makers are integrating chips using schemes. TSV technology enables 3D interconnects by creating vertical pathways functioning as components of the integrated circuit to connect stacked chips or wafers.

The Applied Centura Silvia Etch system is specifically designed for the challenging deep silicon etch required to create the vertical connections between the chips or wafers. It is the only TSV etch system to overcome the tradeoff between profile control and high etch rate faced by conventional methods. The system’s high-density plasma source enables the highest silicon and oxide etch rates for all wafer-level packaging applications.

Silvia leverages Applied’s long-standing experience as a leading-edge innovator and market leader in deep silicon etch and TSV production expertise to optimize the etch performance needed for 3D interconnect etch applications. With etch processes accounting for approximately 15% of the TSV manufacturing sequence, the substantial reduction in cost of ownership derived from Silvia’s throughput and CoC advantage from its consumables-free process kit makes a major contribution to lowering customers’ overall cost of implementing TSV technology.

PRODUCER® AVILA™ PECVD

The Applied Producer Avila PECVD system's family of high quality oxide and nitride films meet the low thermal budgets and high productivity required for TSV and other advanced packaging applications.

TSV fabrication involves thinning device wafers and bonding them to temporary carriers made of glass or silicon. As typical bonding adhesives have thermal budgets of approximately 200ºC, all subsequent processing on these hybrid wafers must be done at very low temperatures. Depositing high quality films at low temperatures requires RF power levels that add considerable heat to the wafer surface. To maintain a consistent wafer temperature, the Avila system is equipped with an active cooling feature, enabling stable substrate temperatures as low as 130ºC.

The Avila system's deposition processes run on the production-proven Twin Chamber® Producer® GT™ platform that can process up to six wafers simultaneously. Not only does the platform demonstrate superior handling of bonded wafers, its flexible architecture can accommodate Applied's complete portfolio of TSV dielectric processes for efficient integration development. Delivering double or triple the throughput of other available systems for low temperature dielectric films, the Producer GT platform also significantly reduces cost of ownership per wafer.

Applied Materials (AMAT.O) will buy Varian Semiconductor Equipment Associates Inc VSEA.O for $4.9 billion, shoring up its lead in the $35 billion global market for chip-making gear while tapping rising demand from smartphone and solar equipment manufacturers.

The world's largest maker of equipment for semiconductor manufacturing will pay a 55 percent premium to Varian's Tuesday closing price to gain control of a small but fast-growing niche market that is pivotal in chipmaking and in which Varian is the dominant technology leader.

Varian's stock jumped 51 percent to close at $61.36 after the $63-per-share deal was announced on Wednesday.

Buying Varian will boost Applied Materials' earnings per share within a year and save up to $60 million annually as the red-hot market for gadgets like Apple's (AAPL.O) iPhone fuels demand for chip manufacturing tools, executives said.

Varian produces ion implantation gear for making integrated circuits, or chips, found in all modern electronic gadgets. It is a complex process of implanting ions around which the structure of the chip is built.

Applied Materials does not currently offer ion implanters, a small but fast-growing part of the global chip-making gear market that will become increasingly crucial as microchip architecture becomes tinier and more complex.

"Varian has been very successful as a company just because of their large market share," said Needham & Company analyst Edwin Mok. "There are plenty of things and cross-selling opportunities they can leverage off each other -- which sort of justifies the price."

Spending on ion implanters accounts for up to 5 percent of the $35 billion wafer fabrication equipment market, said Caris & Co analyst Ben Pang.

The Varian deal comes a month after Texas Instruments TXN.N announced it would acquire National Semiconductor (NSM.N) for $6.5 billion, a 78 percent premium. That agreement would unite two of the industry's oldest companies into a dominant force in analog microchips used in products ranging from phones to cars.

It is Applied Material's largest ever acquisition and will help the company corner a larger share of the equipment market for higher-performance chips, particularly for mobile applications with faster speeds and longer battery life.

Varian's technology could also extend into solar, display and light-emitting diodes, or LEDs, the companies said.

But at about 16 times expected earnings, compared to around 10 times expected earnings of other chip tool makers, the Varian acquisition seems expensive, said RBC Capital analyst Mahesh Sanganeria.

"The case of National Semiconductor was different. The stock was undervalued. I don't think Varian's stock was undervalued by any stretch," Sanganeria said.

Shares of Novellus Systems NVLS.O, another chip-gear maker, jumped 6.5 percent to $32.92 as investors speculated that competitors plump with cash after cutting costs during the recession could make more acquisitions.

"Their business models are working pretty well right now, so what do you do with the cash? Maybe you buy back shares, or you can go out and try to buy a company that will offer you some opportunities to expand your market," said Pacific Crest Securities analyst Weston Twigg.

He pointed to Nanometrics (NANO.O), GT Solar SOLR.O, Rudolph Technologies RTEC.O and Cymer CYMI.O as potential targets.

Varian, whose customers include GlobalFoundries, Hynix Semiconductor (000660.KS), Intel (INTC.O), IBM (IBM.N), Micron Technology (MU.O) and Samsung Electronics (005930.KS), entered the market for ion implanters in 1975 through the acquisition of Extrion Corp.

Also on Wednesday, Intel (INTC.O) Corp previewed its next generation manufacturing technology, giving shares of chip equipment makers support on expectations of more capital spending.

BOOSTER DEAL

Applied Materials sees the Varian purchase adding more than 8 percent to its earnings per share before special items in the first full year.

The company estimates savings from the acquisition at $50 million to $60 million annually, mostly from costs of materials, executives told analysts on a conference call.

"We have a very strong and established global supply chain, and we think there's going to be value that comes out of leveraging that," Applied Materials Chief Financial Officer George Davis said.

The combined company would compete with ASML Holding N.V. (ASML.AS), Tokyo Electron Limited (8035.T), KLA Tencor Corporation (KLAC.O) and Lam Research Corp (LRCX.O).

Applied Materials expects the deal to be reviewed simultaneously by regulators in the United States and other countries but analysts were not concerned about antitrust issues.

Applied expects to fund the deal with cash on hand and debt. It has secured a commitment for $2 billion, one-year bridge loan from JPMorgan Chase Bank (JPM.N), Citigroup Global Markets Inc (C.N) and Morgan Stanley Senior Funding Inc (MS.N).

Credit Suisse (CSGN.VX) acted as financial adviser to Varian.

Varian will have to pay a termination fee of $147 million if it ends the deal, and if agreement fails to get antitrust approvals, Applied will have to pay $200 million, the companies said.

Applied Materials' stock ended 1 percent lower at $15.09.

The Producer InVia system delivers an innovative CVD process that deposits highly conformal and electrically robust dielectric liners in via-first and via-middle TSVs.

For customers diversifying to TSV processing, the InVia system offers not only a benchmark process but demonstrated integration worthiness in the TSV manufacturing sequence. It is the only process that satisfies the thermal budget and conformality requirements for via-middle TSV. The unique deposition process results in film breakdown voltage and leakage current that are significant improvements over the standard specifications.

The InVia system is also uniquely capable of depositing liners as thin as 200nm and as thick as 1µm over a wide range of aspect ratios (6:1 to 11:1).

http://www.appliedmaterials.com/files/nanochip-journals/NanochipTechJournal_Vol11Issue1_2013_Security.pdf#page=11

The Applied Producer Optiva low-temperature CVD system complements Applied Producer InVia™ and Applied Producer Avila™ low-temperature, high-quality oxide and nitride films for TSV and other advanced packaging applications.

The Optiva system deposits a highly conformal, polymer-compatible oxide that can serve as a protective layer on top of the micro-lens in backside illuminated CMOS image sensors (BSI CIS) and as the insulation liner of high aspect ratio TSVs for CIS. TSV fabrication involves thinning device wafers and bonding them to temporary carriers made of glass or silicon. As typical bonding adhesives have thermal budgets of approximately 200ºC, all subsequent processing on these temporarily bonded wafers must be done below 200ºC. BSI CIS necessitates similarly low-temperature processing due to the thermal budget set by the polymer material used for the micro-lens.

The Optiva system also meets other BSI CIS requirements, such as transparency and compatibility with the polymer material of the micro-lens. In addition, the system offers considerable flexibility in modulating film properties and conformality in-situ by combining the superior step coverage obtained with thermal CVD technology and the excellent hermeticity typical of plasma processes. The superior conformality of the deposited film improves light transmission in BSI CIS, which are >50% more sensitive than conventional front-illuminated sensors. Its excellent hermeticity is crucial in protecting the micro-lenses from moisture.

The Optiva system’s deposition processes run on the production-proven Twin Chamber® Producer® GT™ platform that can process up to six wafers simultaneously. Not only does the platform demonstrate superior handling of bonded wafers, its flexible architecture can accommodate Applied's complete portfolio of TSV dielectric processes for efficient integration development. Delivering double or triple the throughput of other available systems for low-temperature dielectric films, the Producer GT platform also significantly reduces cost of ownership per wafer.

The Raider-S is a high-volume single-wafer electroplating tool for TSV and wafer-level packaging applications. It features a fully automated precision wafer handling system and multiple process chambers and is compatible with automated chemical management systems.

Features

Advanced metal deposition or clean chambers 15 to over 27+ process chambers Incorporated chemical analysis options Membrane plating technology Multi-zone anode for thinned seed plating Small footprint 200mm or 300mm wafers Applications ECD

Electrolytic metal deposition (Cu-TSV, Pillar, and SnAg bumping)

Applied Reflexion LK CMP provides production-proven, high performance planarization solutions for copper damascene, shallow trench isolation, oxide, polysilicon, and tungsten applications. Its high-speed planarizing platens and multi-zone polishing heads enable superior uniformity and efficiency with low downforce for extendibility to <45nm device generations.

The integrated post-CMP Desica® cleaner uses unique full-immersion Marangoni® vapor drying technology to virtually eliminate watermark defects and dramatically reduce particle contamination. The wafer is so clean after CMP (<100 45nm defects on a 300mm wafer) that compared to the entire surface area of the earth, the remaining contaminants would cover only 0.3 acres, the size of a medium sized suburban garden.

The Applied Reflexion LK CMP system also implements a full suite of endpoint methods, in-line metrology and advanced process control capabilities that ensure excellent within-wafer and wafer-to-wafer process control and repeatability for all planarization applications. Its patented window-in-pad technology enables accurate real-time polish control of every wafer without compromising throughput. The new FullVision™ in-situ endpoint system, for all stop-in and stop-on dielectric applications, uses broadband spectroscopy to significantly improve Cpk and minimize wafer scrap caused by drifts in consumable sets and incoming wafer variations.